RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
Product ID: B071GY6MND
Condition: USED (All books in used condition)
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Product Description
Condition - Very Good
The item shows wear from consistent use but remains in good condition. It may arrive with damaged packaging or be repackaged.
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
Technical Specifications
Country
USA
Manufacturer
Sutherland HDL, Inc.
Binding
Kindle Edition
ReleaseDate
2017-06-15T06:36:26.000Z
Format
Kindle eBook
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