SystemVerilog Assertions Handbook, 4th Edition: ... for Dynamic and Formal Verification

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

Formal Verification: An Essential Toolkit for Modern VLSI Design

Advanced UVM

Logic Design and Verification Using SystemVerilog (Revised)

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies

Digital Logic RTL & Verilog Interview Questions

The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology